To be part of a highly skilled and challenging high speed PHY design team working on the latest technology nodes (12nm and below).
Contribute to layout design and development leading to high quality IP delivery
Leading, mentoring and coaching junior team members.
Work closely with Analog and PD engineers for design closures.
Pair with similar domain specialists across other geographical locations on core technical initiatives
Equal opportunity position with excellent pay package!
SKILLS required:
Hand on experience of high-speed analog layout including floorplan, power planning, parasitic optimization and device matching.
experience with technology nodes like 16nm and below
Expertise with EDA tools such as virtuoso, extraction and DRC/LVS
Exposure to ESD layouts, EM/IR flows
Proficient with SKILL or one of the scripting languages
Experience of abstract view generation
The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
M.S./MTech, BS/BE, Diploma
Experience Required: 8+ Years
Job Information
Job Type:
Full Time
Industry:Semiconductors/Electronics
Function : Civil & Site/Electrical/Aerospace/Engg Project Management